1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to clock buffer circuits.
2. Description of the Related Art
As electronic circuits increase in density, particularly integrated circuits, power consumption has also increased. In order to minimize power consumption, power management circuitry may be used. Power management circuitry may be used to selectively and/or temporarily remove power from a certain part of an electronic circuit during times while that part is inactive. Alternatively or in addition, conditional clocking schemes may be used.
Conditional clocking may be used to conditionally generate a clock signal to a functional circuit dependent on whether or not the functional circuit is active. If the circuit is active, the clock signal is generated (e.g. rising and falling edges are generated providing a high phase and a low phase of the clock signal). If the circuit is inactive, the clock signal may be inhibited (e.g. held in a constant state instead of toggling high and low). Inhibiting the clock signal during idle times for the functional circuit may result in power savings since the state of the circuit is held steady and thus the circuit may experience minimal switching activity. Typically, the condition input to the conditional clock circuitry (which determines whether the clock signal is generated or inhibited) has a relatively high setup time with regard to an input clock edge, to ensure glitch free operation of the conditional clock signal.
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit configured to precharge a first node and a second node, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, respectively, and a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.
In one embodiment, the clock buffer circuit may be configured to drive a clock signal to functional logic. Power management for the functional logic may be controlled by conditional clocking from the clock buffer circuit. The clock buffer circuit may include a condition input. When a certain condition is asserted on the condition input, the clock buffer circuit may prevent transitions of the output clock signal. This may result in reduced power consumption by the functional logic receiving the output clock signal. When the condition which caused the circuit to inhibit the output clock signal is removed, the clock buffer circuit may once again begin driving the output clock signal to the functional logic.
Thus, in various embodiments, the conditional clock buffer circuit may be used to provide conditional clocking to various logic circuits. The conditional clock buffer circuit may be used in providing fine-grain power management functions to a chip.